Computational power of a computing device can be improved by increasing the operational frequency of the core. Depending on the environment of the computing device, however, the operational frequency may be unable to be increased. And from the viewpoint of power efficiency, there is a limit to improving the performance by increasing the operational frequency. In recent years, as disclosed in Japanese Patent Laid-Open No. 2010-160537, multi-core parallel computing devices with a plurality of cores mounted on a single semiconductor chip have been attracting attention. The multi-core parallel computing devices require lower operational frequency than single-core computing devices, provided that the amount of computation is the same. In addition, since tasks to be processed are allocated to the plurality of cores for parallel computation, the operating time can be reduced compared with the case where a single core performs the computation.
Advantageous applications of such a parallel computing device include a real-time control device. To control the operation or state of a complicated control object, the real-time control device uses a control algorithm that involves many numerical calculations. In particular, with a vehicle control device, which is a kind of the real-time control device, the control algorithm has becoming larger in scale and becoming more complicated year by year in order to meet the market and regulatory requirements. Thus, the operational load is increasing, and a single-core central processing unit (CPU) will probably become unable to complete the computation in the control period. Application of the parallel computing device to the real-time control device is expected as effective means for avoiding such a situation.